LAN91C113-NU

Product Summary

The LAN91C113-NU is an Non-PCI Ethernet Single Chip MAC PHY. The LAN91C113-NU is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C113-NU is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications. The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations. The LAN91C113-NU is software compatible with the LAN9000 family of products.

Parametrics

LAN91C113-NU absolute maximum ratings: (1)Operating Temperature Range: 0℃ to +85℃; (2)Storage Temperature Range: -55℃ to + 150℃; (3)Lead Temperature Range (soldering, 10 seconds): +325℃; (4)Positive Voltage on any pin, with respect to Ground: VCC+ 0.3V; (5)Negative Voltage on any pin, with respect to Ground: -0.3V; (6)Maximum VCC: +5V.

Features

LAN91C113-NU features: (1)Single Chip Ethernet Controller; (2)Dual Speed - 10/100 Mbps; (3)Fully Supports Full Duplex Switched Ethernet; (4)Supports Burst Data Transfer; (5)8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers; (6)Enhanced Power Management Features; (7)Optional Configuration via Serial EEPROM Interface; (8)Supports 8, 16 and 32 Bit CPU Accesses; (9)Internal 32 Bit Wide Data Path (Into Packet Buffer Memory); (10)Early TX, Early RX Functions; (11)Built-in Transparent Arbitration for Slave Sequential Access Architecture; (12)Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues; (13)3.3V Operation with 5V Tolerant IO Buffers (See Pin List Description for Additional Details); (14)Single 25 MHz Reference Clock for Both PHY and MAC; (15)External 25Mhz-output pin for an external PHY supporting PHYs physical media; (16)Low Power CMOS Design.

Diagrams